It is common in digital systems to have a master clock signal that controls the overall operation of the digital logic circuits used. In many systems, it is important that the various parts remain synchronized. This type of design is commonly referred to as a synchronous system. Typically this is achieved by having a single clock signal control the entire system, as is done in many systems.
In many systems, however, only a portion of the logic is required to be fast, and the remainder could potentially run slower. But the use of a single clock forces all the logic to be the same fast speed. The clock rate required by the fastest portion of the system may require the use of faster, more expensive components than otherwise would be necessary in the portions of the logic that could have been slower, but must be run faster to use the same clock. Also, because a portion of the logic is run faster than needed, the power consumption and unwanted radio emissions may also be greater.
To avoid these disadvantages, some designs are implemented as nearly synchronous, with two different clock signals that are nearly synchronized. Referring now to the drawing, and in particular to FIG. 1, a typical digital logic system is referred to generally by reference numeral 10. Digital logic system 10 includes a subsystem 12 of logic that is required to be run fast, and a subsystem 14 of logic that may be run more slowly. A circuit 16 provides the fast clock for subsystem 12 that requires it; this interconnecting clock signal 18 will be referred to as CLOCKA. CLOCKA is also used as an input to a frequency divider circuit 20 which generates an output signal 22, which will be referred to as CLOCKB, which is used to drive slower subsystem 14. All systems with this design suffer from a certain amount of time lag between CLOCKA and CLOCKB, a characteristic known as clock skew. Digital systems typically can not tolerate a significant amount of clock skew. Signals 24, which will be referred to as DATA, and 26, pass between subsystems of logic with different clock skew and can cause the logic to malfunction under certain common and typical conditions.
Referring now to FIG. 2, typical digital logic waveforms graphed as signal level variations over a period of time are referred to generally by reference numeral 30. These waveforms include a typical CLOCKA clock signal 32 which periodically changes from a high to a low state. CLOCKB clock signal 34 also periodically changes from a high to a low state, but at a slower rate, in the case illustrated, the rate is 1/2 of CLOCKA. Because the frequency divider circuit requires a certain amount of time from when the CLOCKA input changes to when it changes the CLOCKB output, there is a certain time lag 36 and 38 between the low-to-high transition of CLOCKA and the transition of CLOCKB. This time lag is referred to as the clock skew. In other systems it may be based on the high-to-low transition of CLOCKA, but the principle remains the same, the transitions of CLOCKB do not quite occur at the same time as the transitions of CLOCKA. A potential malfunction can occur when DATA signal 40 transition occurs as a result of CLOCKA, and its state is used by logic that is based on CLOCKB. Ideally, changes in the DATA signal would not be recognized until CLOCKB transition 42. However, because the DATA signal also requires a certain, but not absolutely predictable, amount of time to change from low-to-high after the CLOCKA input transition, it may be impossible to predict whether the DATA signal will be low or high at the CLOCKB low-to-high transition 44. When this happens, the digital logic that runs with CLOCKB and uses DATA as an input may act unpredictably, a condition known as metastability. Such an occurrence can cause a system malfunction.
Another concern is the other signal 26 in FIG. 1 which is output by the slower logic subsystem 14 and enters into the fast logic subsystem 12. Because of the clock skew, this signal has less time between the CLOCKB transition and the next CLOCKA transition, and therefore must be even faster than the signals in the fast logic subsystem so as to not cause a malfunction.
Prior art includes a variety of techniques to keep the clock skew to a minimum and thus reduce the chance of a malfunction. Such techniques include implementing the frequency divider so that the skew is minimum, such as using very fast logic dividers or a phase-lock-loop circuit. Other techniques rely on the use of delay lines or clock drivers to keep both clocks nearly in synchronization. In some cases, the technique may even reverse the time lag such that the CLOCKB transition is slightly before the CLOCKA transition, but this does not solve the problem, it only exchanges the two concerns of signals 24 and 26. All of these methods simply reduce clock skew, they do not completely eliminate it. Also, they are difficult to control over a wide-range of components, time and temperature and may require production-line tweaking or use costly and complex components, and often produce inconsistent clock skews.